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Schematic Integrity Analysis : ウィキペディア英語版 | Schematic Integrity Analysis
Schematic Integrity Analysis is a term coined by (Valydate Inc. ) founders Michael Alam and Mark Cianfaglione in March 2010 to describe an automated verification approach that detects errors in electronic schematic designs. ==Technology==
Valydate has created a proprietary SW application called "ValydateDesign". This application contains a rules library which tests each net in an emerging design according to the connections prescribed by the design's netlist and using advanced component models derived from manufacturer's datasheets. The analysis technique can be applied to single or multiple interconnected designs. The assessment takes less than 10 working days to complete, and is normally applied immediately prior to PCB layout design.
抄文引用元・出典: フリー百科事典『 ウィキペディア(Wikipedia)』 ■ウィキペディアで「Schematic Integrity Analysis」の詳細全文を読む
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